Simulation Options
The .OPTIONS statement controls simulation accuracy, convergence behavior, and general parameters.
.OPTIONS RELTOL=1e-4 ABSTOL=1e-14 TEMP=85
Options can appear on one line or across multiple .OPTIONS statements. When the same option is set more than once, the last value wins.
Convergence Options
These options control the Newton-Raphson iteration loop used to solve nonlinear circuit equations at each operating point or timestep.
Tolerances
| Option | Default | Unit | Description |
|---|---|---|---|
| ABSTOL | 1e-12 | A | Absolute current tolerance. NR iteration converges when all branch current changes are below this value. |
| RELTOL | 1e-3 | -- | Relative tolerance. NR converges when all variable changes are below `RELTOL * max( |
| VNTOL | 1e-6 | V | Absolute voltage tolerance. Combined with RELTOL to determine voltage convergence. |
| CHGTOL | 1e-14 | C | Absolute charge tolerance. Used in transient analysis for charge-conservation convergence. |
Iteration limits
| Option | Default | Description |
|---|---|---|
| ITL1 | 100 | Maximum iterations for DC operating point. If NR does not converge in this many iterations, the simulator applies GMIN stepping or source stepping. |
| ITL2 | 50 | Maximum iterations for each DC sweep point. |
| ITL4 | 10 | Maximum iterations per transient timepoint. If NR does not converge, the timestep is reduced and the step is retried. |
GMIN
| Option | Default | Unit | Description |
|---|---|---|---|
| GMIN | 1e-12 | S (mho) | Minimum conductance added to every node. Prevents singular matrices from floating nodes. Also used in GMIN stepping for DC convergence. |
Convergence algorithm
The Newton-Raphson loop at each point checks two conditions:
- Voltage convergence: for each node voltage V,
- Current convergence: for each branch current I,
Both conditions must be satisfied for convergence.
When DC operating point fails to converge within ITL1 iterations, spice-rs applies:
- GMIN stepping: progressively reduces the GMIN conductance from a large value down to the user-specified GMIN
- Source stepping: if GMIN stepping fails, ramps all sources from 0 to their final values
Transient Options
These options control the numerical integration method and timestep selection during .TRAN analysis.
Integration method
| Option | Default | Values | Description |
|---|---|---|---|
| METHOD | TRAP | TRAP, GEAR | Integration method. TRAP (trapezoidal) is second-order and the default. GEAR (Gear/BDF) is available at orders 1-6. |
| MAXORD | 2 | 1-6 | Maximum order for Gear integration. Ignored when METHOD=TRAP. Higher orders allow larger timesteps but may introduce ringing on sharp transitions. |
Timestep control
| Option | Default | Unit | Description |
|---|---|---|---|
| TRTOL | 7 | -- | Transient error tolerance factor. Multiplies the LTE estimate to determine whether a timestep is accepted. Higher values allow larger timesteps (less accurate). Lower values force smaller steps (more accurate). |
| CHGTOL | 1e-14 | C | Charge tolerance for LTE-based timestep control. |
How timestep control works
At each transient timepoint, the simulator:
- Solves the NR equations at the trial timestep
- Estimates the local truncation error (LTE) of each state variable
- Compares LTE against
- If LTE is too large, rejects the step and retries with a smaller timestep
- If LTE is small enough, accepts the step and may increase the timestep for the next point
The maximum internal timestep is bounded by the .TRAN tmax parameter (default: tstop/50).
Trapezoidal vs Gear
| Property | Trapezoidal | Gear (order 2) |
|---|---|---|
| Accuracy | Second-order | Second-order |
| Stability | A-stable | A-stable |
| Ringing | Can produce numerical ringing on stiff systems | No ringing |
| Damping | No numerical damping | Some numerical damping |
| Typical use | General purpose | Switching circuits, stiff systems |
For circuits with sharp switching edges (digital logic, power converters), METHOD=GEAR with MAXORD=2 can avoid spurious oscillations that trapezoidal integration may produce.
General Options
Temperature
| Option | Default | Unit | Description |
|---|---|---|---|
| TEMP | 27 | C | Circuit simulation temperature. All device models are evaluated at this temperature. |
| TNOM | 27 | C | Nominal temperature at which model parameters were measured. Device models use TNOM as the reference point for temperature scaling. |
Temperature affects:
- Thermal voltage:
- Junction saturation currents (IS, ISE, ISC)
- Mobility (U0)
- Threshold voltage (VTO, VTH0)
- Resistance (RD, RS, RE, RC, RB)
Pivot tolerances
| Option | Default | Unit | Description |
|---|---|---|---|
| PIVTOL | 1e-13 | -- | Absolute minimum pivot value for the sparse matrix solver. Elements smaller than this are treated as zero during factorization. |
| PIVREL | 1e-3 | -- | Relative pivot tolerance. During factorization, a pivot is accepted if it exceeds PIVREL * max_element_in_column. Smaller values allow more fill-in but may improve accuracy. |
Other
| Option | Default | Description |
|---|---|---|
| NOOPITER | off | Skip the DC operating point iteration (use initial conditions directly). Rarely used. |
| KEEPOPINFO | off | Retain the operating point information in memory for post-analysis queries. |