The MOSFET

The metal-oxide-semiconductor field-effect transistor is the most manufactured object in human history. Every processor, every memory chip, every system-on-chip is built from billions of them. If you understand the MOSFET, you understand the atom of digital logic.

At its heart, a MOSFET is a voltage-controlled valve. Apply a voltage to the gate, and current flows between drain and source. Remove the voltage, and the valve shuts off. That is the entire story of digital switching -- and the beginning of a much richer analog story.

A MOSFET has four terminals: gate, drain, source, and bulk (substrate). The gate is separated from the channel by a thin oxide layer -- this is the "insulator" in the "metal-oxide-semiconductor" sandwich. No DC current flows into the gate. The device is controlled entirely by the electric field that the gate voltage creates across the oxide.

MOSFETs come in two complementary types:

• NMOS (N-channel): turns on when (gate positive relative to source). Electrons carry current.
• PMOS (P-channel): turns on when (gate negative relative to source). Holes carry current.

Every equation in this chapter is written for NMOS. For PMOS, flip the sign of all voltages and currents. SPICE handles this internally -- in spice-rs, the MosfetType enum carries the polarity factor that gets multiplied through the equations.

Three Regions of Operation

Every MOSFET model -- from the simplest textbook equation to BSIM4's five thousand lines of code -- begins with the same question: which region is this device operating in?

The answer depends on just two voltages: (gate-to-source) and (drain-to-source), measured relative to one parameter: (threshold voltage).

Cutoff (): The gate voltage is too low to form a conducting channel. No current flows. The device is off.

Linear / Triode ( and ): The channel exists from source to drain. Current increases roughly linearly with . The device behaves like a voltage-controlled resistor.

Saturation ( and ): The channel is "pinched off" near the drain. Current no longer increases with -- it depends only on . The device behaves like a voltage-controlled current source.

The three equations

For an NMOS with threshold voltage and transconductance parameter :

Cutoff ():

Linear (, ):

Saturation (, ):

These are sometimes called the "square-law" equations because of the quadratic dependence on gate overdrive in saturation.

The I-V family

If you sweep from 0 to some maximum for several fixed values of , you get the characteristic I-V family of curves. Each curve rises steeply in the linear region, then flattens in saturation. The boundary between regions is the parabola .

In reality, the saturation curves are not perfectly flat -- they have a slight upward slope due to channel-length modulation (the parameter).

Drag the sliders above to see how threshold voltage, transconductance, and channel-length modulation shape the I-V characteristics. Increasing tilts the saturation curves upward -- the device has a finite output resistance .

A circuit to see it

Here is an NMOS with a drain resistor, forming the simplest common-source configuration. The operating point lies where the device's I-V curve intersects the load line set by RD and VDD.

With = V and V, the device is . Whether it sits in the linear or saturation region depends on , which is set by the current through RD. SPICE solves this nonlinear system using Newton-Raphson iteration.

Why regions matter for simulation

Newton-Raphson needs derivatives. The drain current equation and its partial derivatives (, ) have different forms in each region. At every iteration, the simulator must:

1. Check which region the device is in
2. Evaluate , , and using that region's equations
3. Stamp these into the MNA matrix
4. Solve and iterate

Getting the region boundaries right -- and making the transitions smooth -- is one of the most important details in MOSFET modeling. A discontinuity at a region boundary can cause Newton-Raphson to oscillate endlessly between two regions, never converging.

Level 1: The Shichman-Hodges Model

The Level 1 MOSFET model is the simplest model that a SPICE simulator actually uses. Published by Shichman and Hodges in 1968, it captures the essential physics -- threshold, square-law current, and channel-length modulation -- in four core parameters.

The four core parameters

The effective gain factor is:

The equations

Cutoff ():

Linear ( and ):

Saturation ( and ):

Notice the factor. This is channel-length modulation -- the slight increase of drain current with in saturation. Without it (), the saturation current would be perfectly flat. With it, the I-V curves have a small upward slope, and the device has a finite output resistance:

We write rather than because the threshold voltage is modified by the body effect. When , .

How Level 1 stamps into the MNA matrix

SPICE does not plug the equation directly into the matrix. Instead, it linearizes the device around its current operating point using a Newton-Raphson companion model. The MOSFET becomes a small-signal equivalent circuit:

Three elements stamp into the matrix:

1. -- output conductance (drain-source conductance), stamps like a resistor between drain and source
2. -- a voltage-controlled current source from drain to source, controlled by
3. -- an equivalent current source that accounts for the difference between the full nonlinear current and the linearized approximation

The partial derivatives in each region:

Linear region:

Saturation region:

The equivalent current

The equivalent current source ensures that the linearized model produces the correct total current at the current operating point:

What Level 1 gets right and wrong

Gets right: basic switching behavior, DC operating point for hand calculations, qualitative I-V characteristics, the structure of MNA stamping that all models share.

Gets wrong: no velocity saturation, no subthreshold conduction, poor modeling of short-channel effects, oversimplified capacitances.

Level 1 is the pedagogical model: learn here, then graduate to BSIM3 for real design work. But every BSIM3 simulation still evaluates region, computes current, takes derivatives, and stamps -- the same four steps, just with more physics inside each one.

The Body Effect

In textbook circuits, the MOSFET source is connected to the substrate (bulk). In real circuits, it often is not. When , the threshold voltage shifts -- and this shift can be large enough to change the operating region of the device.

This is the body effect, and it is governed by two parameters: GAMMA () and PHI ().

The physical intuition

The gate voltage creates an electric field that pushes carriers away from the surface, forming the depletion region that precedes channel formation. But the substrate has its own potential. If the source is lifted above the substrate (, which means for NMOS), the depletion region under the gate widens.

A wider depletion region means more charge that the gate must overcome before a channel forms. So the threshold voltage increases. Think of it this way: the substrate is a "back gate." Making more negative is like pulling the threshold voltage higher.

The equation

The modified threshold voltage is:

where:

For NMOS, in normal operation, so , and the body effect always increases above .

How large is the shift?

Consider V, V, V:

A threshold shift of 335 mV -- nearly half the value. This is not a minor correction.

The gmbs transconductance

The body effect introduces a third transconductance into the small-signal model:

This stamps into the MNA matrix as a voltage-controlled current source between drain and source, controlled by . The equivalent current source becomes:

Connection to process parameters

GAMMA and PHI are not arbitrary fitting parameters -- they come from the fabrication process:

where is the substrate doping concentration, is the oxide capacitance per unit area, and is the intrinsic carrier concentration. Higher doping means a larger GAMMA and a stronger body effect. Thinner oxide means larger , which reduces GAMMA.

Capacitances

Up to this point, we have treated the MOSFET as a purely resistive device: apply voltages, get current. But MOSFETs store charge -- in the gate oxide, in the depletion regions, in the junctions. These stored charges create capacitances that determine how fast the device can switch.

For DC analysis, capacitances do not matter. For transient and AC analysis, they are everything.

Two families of capacitance

Gate capacitances (, , ) arise from charge stored in the gate oxide and channel. They depend on the operating region -- in a way that is surprisingly discontinuous.

Junction capacitances (, ) arise from the reverse-biased PN junctions between the source/drain diffusions and the substrate. They behave like standard diode junction capacitances.

The Meyer model for gate capacitances

The Meyer model (1971) partitions the total gate capacitance into three components that vary with operating region. The total gate oxide capacitance is:

Cutoff (): , , . All the gate capacitance is between gate and bulk.

Linear (): The channel shields the gate from the bulk, so drops to zero. The oxide capacitance is shared between and .

Saturation (): , , . The channel is pinched off at the drain end.

The discontinuity problem

At the transition from linear to saturation, drops abruptly from a nonzero value to zero. This discontinuity in capacitance means a discontinuity in charge, which creates a nonphysical spike in current during transient analysis. More advanced models (Ward-Dutton, used in BSIM3/4) work with charges directly and take derivatives numerically, avoiding this problem.

Junction capacitances

The source-bulk and drain-bulk junctions are reverse-biased PN junctions. Their capacitance follows the standard depletion capacitance formula:

The total junction capacitance for the source is:

where is the source area, is the source perimeter, and is the sidewall capacitance per unit length.

Why capacitances determine speed

The propagation delay of a CMOS inverter is dominated by the time it takes to charge and discharge the load capacitance through the MOSFET:

Every picofarad in the model directly translates to picoseconds of delay.

Level 2 and Level 3

Level 1 captures the textbook MOSFET: square-law current, channel-length modulation, body effect. But real silicon departs from the square law in important ways, especially as channel lengths shrink. Level 2 and Level 3 bridge the gap between the pedagogical model and the empirical models (BSIM3/4) that foundries provide.

Level 2: physics-based corrections

Velocity saturation (VMAX): In short channels, carriers reach their maximum drift velocity before pinch-off occurs. The saturation voltage drops:

This is the single most important correction for short-channel devices.

Subthreshold conduction (NEFF): Level 1 has a hard cutoff at . In reality, current drops exponentially below threshold:

Mobility degradation (UCRIT, UEXP): Carrier mobility decreases under high vertical electric fields:

Level 3: semi-empirical simplification

Level 3 addresses the same physical effects as Level 2 but uses simpler, semi-empirical formulas:

Simplified saturation voltage:

Empirical mobility model:

One parameter () instead of Level 2's two.

When to use which

Neither Level 2 nor Level 3 is used much in modern design. They occupy a historical middle ground. In practice, foundries supply BSIM3 or BSIM4 model cards. Level 2 and 3 exist in spice-rs for compatibility with legacy netlists and for educational value.

BSIM3v3: The Industry Standard

The Berkeley Short-channel IGFET Model, version 3 (BSIM3v3), is the most widely used MOSFET model in the semiconductor industry. When a foundry gives you a "model card" for their process, it is almost certainly BSIM3 or its successor BSIM4.

BSIM3 is not an incremental improvement over Level 1-3. It is a fundamentally different approach: 150+ parameters organized into groups, each group capturing a specific physical effect at sub-micron dimensions.

The critical short-channel effects

Drain-Induced Barrier Lowering (DIBL): The drain voltage lowers the source-channel barrier, reducing the effective threshold by hundreds of millivolts at 0.25 m.

Channel-Length Modulation (CLM): BSIM3 models the actual depletion region extension near the drain, which depends nonlinearly on bias.

Velocity Saturation: Carriers reach maximum velocity in very short channels, making the I-V characteristics more linear than quadratic.

Quantum Mechanical Effects: At thin oxide thicknesses (<5 nm), quantum confinement pushes the inversion layer charge away from the interface.

The unified current equation

Unlike Level 1-3, which have separate equations for linear and saturation, BSIM3 uses a single equation that smoothly transitions between regions:

The structure reveals the key ideas: the square law, the smooth velocity-saturation transition, field-dependent mobility, process-corrected dimensions, and parasitic resistance.

Capacitance model

BSIM3 replaces the Meyer capacitance model with a charge-based model. Instead of computing capacitances directly, it computes the charges on each terminal () and takes numerical derivatives:

This guarantees charge conservation across region boundaries, eliminating the spurious current spikes that plague the Meyer model.

BSIM4

BSIM4 is the successor to BSIM3v3, extending the model to deep sub-micron technology nodes (90 nm and below). With 200+ parameters and approximately 5000 lines of code in spice-rs, it is the most complex device model in the simulator.

What BSIM4 adds

Gate leakage current: Below approximately 2 nm oxide thickness, quantum mechanical tunneling allows current through the gate oxide.

Stress effects: Mechanical stress in the silicon lattice changes carrier mobility. Modern processes intentionally apply stress to boost performance.

New noise models: Improved flicker noise models and induced gate noise for RF applications.

FinFET support: Starting with BSIM4 version 4.8, support for non-planar transistor geometries.

Most foundries at 90 nm and below provide BSIM4 exclusively. The porting strategy in spice-rs is direct translation from the reference C code -- the model is too complex for independent re-derivation.

CMOS Circuits

Everything in the previous sections -- regions of operation, Level 1 equations, body effect, capacitances -- comes together in CMOS circuits. Complementary MOS pairs an NMOS and a PMOS to build logic gates that consume almost no static power and switch cleanly between supply rails.

The CMOS inverter

An NMOS pull-down and a PMOS pull-up, sharing the same gate input:

The elegance of CMOS: when the input is low, M1 is off and M2 is on, pulling the output to VDD. When the input is high, M1 is on and M2 is off, pulling the output to ground. In both stable states, no DC current flows from VDD to ground. Power is consumed only during switching.

The transfer characteristic

Sweeping from 0 to VDD produces the voltage transfer characteristic (VTC). The switching threshold is controlled by the relative strengths of M1 and M2. For a symmetric inverter, the NMOS and PMOS are sized so that the switching threshold is at .

The dashed blue line marks the current value. Drag the Vin slider to trace along the transfer characteristic.

Transfer Characteristic (SPICE DC Sweep)

The VTC above was computed from the simplified square-law equations in JavaScript. Now let's run the actual SPICE simulator with a DC sweep and see the real transfer characteristic, including all the Level 1 model details that the simplified code omits.

The SPICE DC sweep solves the full nonlinear circuit at each input voltage. The dashed gray line is -- the switching threshold is where the VTC crosses this line. With the asymmetric sizing (KP_N = 110 A/V, KP_P = 55 A/V), the threshold shifts from because the NMOS is stronger than the PMOS. To center the threshold, you would double the PMOS width.

The steep transition region in the middle is where the inverter has high gain -- both transistors are in saturation simultaneously, and a small change in causes a large change in . This is also the region where the circuit is most sensitive to noise, which is why digital designers define noise margins relative to the VTC slope.

Power dissipation

CMOS power has three components:

Dynamic power: -- energy to charge and discharge capacitances.

Short-circuit power: During the input transition, both transistors are briefly on simultaneously. Typically 10-15% of dynamic power.

Leakage power: Subthreshold current when devices are "off." At advanced nodes, this can rival dynamic power. Accurate subthreshold modeling (BSIM3/4) is essential for predicting leakage.

In spice-rs

The MOSFET device models live in the following source files:

Each model implements the same trait -- it computes drain current, transconductances, and capacitance charges given the terminal voltages, then stamps those into the MNA matrix. The progression from Level 1 to BSIM4 is not a change in architecture; it is a refinement of the physics inside the same computational structure.