The JFET

The junction field-effect transistor is the oldest type of FET, predating the MOSFET by several years. It is a depletion-mode device: it conducts with zero gate voltage and is turned off by applying a reverse bias to the gate. This is the opposite of the MOSFET, which is normally off and must be turned on.

JFETs occupy a small but important niche. They appear in the input stages of precision op-amps (extremely high input impedance with low noise), in voltage-controlled resistors, and in discrete RF amplifiers. They are simpler than MOSFETs to model -- the SPICE JFET model has fewer than 10 core parameters.

The physical structure

The gate is a PN junction formed directly against the channel. Reverse-biasing the gate ( for N-channel) widens the depletion region, squeezing the channel and reducing current. At (the pinch-off voltage, which is negative for N-channel), the channel is completely pinched off.

No oxide layer. No insulator. The gate is a reverse-biased diode -- which means the gate draws a tiny leakage current (picoamps at room temperature), but far less than a BJT's base current.

The two types

N-channel JFETs are far more common than P-channel, just as NMOS is more common than PMOS.

The Pinch-Off Model

The SPICE JFET model is compact: three core DC parameters, two junction capacitance parameters, and a handful of parasitic resistances.

The three regions

For an N-channel JFET with (e.g., V):

Cutoff ():

Linear ( and ):

Saturation ( and ):

The parameters

Note that BETA here is the total transconductance coefficient, not as in the MOSFET. The JFET model does not separate process parameters from geometry.

Comparing JFET and MOSFET Level 1

The equations are structurally identical, but the operating philosophy is inverted:

• MOSFET (enhancement, NMOS): V (positive). Off at . Turn on by raising above .
• JFET (depletion, N-channel): V (negative). On at . Turn off by lowering below .

Transconductances

The partial derivatives for the MNA stamps follow the same pattern as MOSFET Level 1:

Saturation region:

These stamp into the MNA matrix exactly as described in the MOSFET chapter: as a voltage-controlled current source, as an output conductance, plus an equivalent current source.

Gate junction capacitances

Unlike the MOSFET (where the gate is insulated), the JFET gate forms a PN junction with the channel:

These are standard reverse-biased junction capacitances. There is no gate oxide capacitance and no body effect.

JFET Circuits

The JFET's depletion-mode behavior -- conducting at zero gate voltage -- gives it a unique role in circuit design. Where MOSFETs and BJTs need bias circuits to turn them on, a JFET can be used with minimal surrounding components.

The self-biased amplifier

The most common JFET amplifier uses self-biasing: a source resistor sets the gate-source voltage without requiring a separate bias supply. With the gate tied to ground through a large resistor, the current through RS creates a positive voltage at the source. Since , this means -- a negative value that partially pinches off the channel.

The small-signal voltage gain is:

If is bypassed with a capacitor, the gain becomes simply .

JFET as a voltage-controlled resistor

In the linear region ( small), the JFET behaves as a resistor whose value is controlled by :

This makes the JFET useful as an analog switch or variable attenuator. At , the resistance is at its minimum. As approaches , the resistance rises toward infinity. Automatic gain control (AGC) circuits exploit this property.

JFET amplifier topologies

The JFET's advantage over the MOSFET in these configurations is lower noise at low frequencies (no oxide interface means no 1/f noise from interface traps) and higher input impedance than the BJT. This is why JFET input stages appear in precision instrumentation amplifiers and low-noise preamplifiers.

In spice-rs

The JFET model lives in device/jfet.rs. It is the most compact device model in the simulator. The load function determines the region, computes , , , gate junction charges, and stamps into the MNA matrix. The simplicity of the JFET model makes it an excellent starting point for understanding how any device model interfaces with the simulator. The same structure -- region selection, current computation, derivative computation, matrix stamping -- appears in every device, from the JFET's 100 lines to BSIM4's 5000.